
module Top(
    output      WE_s,  
    output      RE_s,   
    output      CLE,    
    output      ALE,   
    inout[7:0]  DQ,    
    input       RB,     
    output      WP_s, 


    input clk,
    input clkx2,
    input rst_n
);

parameter CMD_Reset =               8'hFF;
parameter CMD_ReadID =              8'h90;
parameter CMD_ReadStatus =          8'h70;
parameter CMD_ReadPage_C0 =         8'h00;
parameter CMD_ReadPage_C1 =         8'h30;
parameter CMD_ReadPageCache =       8'h31;
parameter CMD_ReadPageCacheCast =   8'h3f;
parameter CMD_ReadMul_C0 =          8'h00;
parameter CMD_ReadMul_C1 =          8'h32;
parameter CMD_ProgPage_C0 =         8'h80;
parameter CMD_ProgPage_C1 =         8'h10;
parameter CMD_ProgPageCache_C0 =    8'h80;
parameter CMD_ProgPageCache_C1 =    8'h15;
parameter CMD_ProgPageMul_C0 =      8'h80;
parameter CMD_ProgPageMul_C1 =      8'h11;
parameter CMD_EraseBlock_C0 =       8'h60;
parameter CMD_EraseBlock_C1 =       8'hD0;
parameter CMD_EraseMul_C0 =         8'h60;
parameter CMD_EraseMul_C1 =         8'hD1;

parameter State_command =   3'b000;
parameter State_adderss =   3'b001;
parameter State_WriteData = 3'b010;
parameter State_ReadData  = 3'b011;
parameter State_Idle =      3'b100;

wire WE_s_m;
wire RE_s_m;
wire CLE_m;
wire ALE_m;
wire[7:0] DQ_m;
wire RB_m;
wire WP_s_m;
wire[7:0] data_m;
wire[2:0] cmd_m;
wire ready_m;

reg[7:0] data_r;
reg[2:0] cmd_r;

assign cmd_m = cmd_r;
assign data_m = data_r;
assign WE_s = WE_s_m;
assign RE_s = RE_s_m;
assign CLE = CLE_m;
assign ALE = ALE_m;
assign DQ = DQ_m;
assign RB = RB_m;
assign WP_s = WP_s_m;

Async_port u_Async_port(
	.WE_s     (WE_s_m     ),
    .RE_s     (RE_s_m     ),
    .CLE      (CLE_m      ),
    .ALE      (ALE_m      ),
    .DQ       (DQ_m       ),
    .RB       (RB_m       ),
    .WP_s     (WP_s_m     ),

    .clk      (clk       ),
    .isEDO    (1'b0      ),
    .rst_n    (rst_n     ),
    .en       (1'b1      ),
    .Cmd      (cmd_m     ),
    .Data     (data_m    ),
    .ready    (ready_m     )
);

reg [7:0] test;

always @(posedge clk or negedge rst_n) begin
    if (rst_n != 1'b0) begin
        cmd_r <= State_WriteData;
        data_r <= test;
        test <= test + 1'b1;
    end else begin
        test <= 8'h00;
    end
end

endmodule // Top